Analog Layout Design Engineer

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoC—faster.

We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

Analog & Mixed-Signal Senior Layout Design Engineer

In this role, you will collaborate in the development of advanced analog integrated circuit designs using best-in-class Synopsys suite of tools. You will be working with local and global teams in developing layout for complex mixed-signal designs in the latest technology nodes. As a member of our Solutions IP Design Group, you would be working as part of a highly experienced mixed-signal layout design team, targeting the next generation NRZ and PAM-based SerDes products. Working experience on multi-Gbps NRZ & PAM4 SERDES layout is a strong plus.

Main responsibilities:

• Design and development of transistor-level analog and mixed signal layout.
• Device/block level floorplan, placement, routing, and physical verification.
• Troubleshoot physical verification issues to get clean and desired results.
• Creating and reviewing layout documents to ensure they meet quality standards and are delivered on time.
  
  

Key Qualifications:

• MSEE or BSEE with a minimum of 2 years of related experience.
• In depth familiarity with layout of analog and mixed signal CMOS circuits.
• Experience in development of SERDES subcircuit layout (ie. RX, TX, PLL, etc.).
• Experience in the following layout design techniques:
• Optimization for signal integrity (ie. clock/data routes, differential routing, shielding).
• Implementation of ESD design constraints, latch-up risk mitigation.
• Familiarity with custom digital layout (logic cell layout and associated logic path routing).
• Layout design for reliability (ie. EM, IR, etc.).
• Design to optimize parasitic layout effects (ie. matching, reliability, proximity effects, etc.).
• Familiarity in design for porting techniques.
• Full custom analog layout design tool: Custom Compiler (or equivalent).
• Verification tools: ICV, Calibre, Star-RCXT, PERC.
• Experience in working with Jira/Atlassian (or other such) tools.
• Strong working knowledge of MS Office Suite of applications.
• Experience with TCL, SKILL, PERL, Python or other language scripting is a plus.
  
  

The base salary range across Canada for this role is between $84,000 to $124,000. In addition, this role may be eligible for an annual bonus, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact [email protected]