ASIC or FPGA Digital Design, Staff or Sr.Staff Engineer

Synopsys Inc


Date: 2 hours ago
City: Ottawa, ON
Contract type: Full time
Key Qualifications

  • BSEE or MSEE with relevant digital design experience in the industry
  • Must be familiar with Verilog and VCS.
  • Good knowledge of back-end synthesis tools DC/PT is desirable.
  • Scripting experience in Shell, Perl, Python and TCL is a plus.
  • Good theoretical and practical knowledge of digital signal processing and data recovery circuits is desirable.
  • Good communication skills for interacting between different design groups and customer support teams are required
  • Must be self-motivated, proactive, and able to apply good design quality while meeting tight deadlines
  • Resolves issues in inventive ways and exercises sound judgment in selecting methods and techniques to obtain solutions.

Preferred Experience

  • RTL coding, modeling of analog blocks, and writing complex system-level test-benches in Verilog.
  • Strong experience of ASIC Digital Design, front end experience.
  • Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures.
  • Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools.
  • Enhancing and maintaining existing SERDES PHY IP.
  • Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams

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