Senior Staff Analog Design Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an expert analog design engineer with a passion for high-speed integrated circuits and a drive to push the boundaries of SERDES technology. You thrive in fast-paced, collaborative environments where your technical insight and leadership make a tangible impact. You possess a deep understanding of CMOS fundamentals and a proven track record in developing robust, high-performance analog and mixed-signal solutions in advanced process nodes. Your experience spans the full design cycle—from conceptual architecture through post-silicon validation—and you are adept at navigating challenges in power, area, and performance optimization.

As a natural mentor and technical leader, you guide junior engineers, foster team growth, and contribute to a culture of innovation and excellence. You are comfortable presenting complex technical concepts both internally and externally, distilling simulation data and customer feedback into actionable design improvements. Your communication skills are top-tier, enabling you to bridge cross-functional teams and align project goals. You continually seek out novel solutions and are motivated by the opportunity to influence both project direction and organizational success. Your attention to detail, ownership mindset, and commitment to quality position you as a trusted leader in the analog design community.

What You’ll Be Doing:

• Reviewing SERDES standards to develop innovative transceiver architectures and sub-block specifications for Multi-Gbps NRZ & PAM4 SERDES IP.
• Investigating and architecting advanced circuit solutions to overcome bottlenecks, achieving breakthroughs in power efficiency, area reduction, and performance.
• Collaborating with cross-functional teams—including analog, digital, and layout engineers—to optimize design and verification strategies for superior quality and project efficiency.
• Presenting and critically reviewing simulation data within project teams and at external industry panels or customer meetings.
• Overseeing physical layout to minimize parasitics, device stress, and process variations, ensuring robust manufacturability and reliability.
• Documenting design features, creating comprehensive test plans, and ensuring traceability throughout the development lifecycle.
• Consulting on electrical characterization of SERDES IP, analyzing customer silicon data, and proposing enhancements or post-silicon updates as needed.
  
  

The Impact You Will Have:

• Driving the next generation of high-speed data communication through pioneering SERDES architectures.
• Enabling Synopsys customers to achieve industry-leading performance, power efficiency, and reliability in their products.
• Fostering a culture of technical excellence and innovation within a diverse, high-caliber design team.
• Accelerating project timelines by streamlining design and verification methodologies.
• Enhancing the overall quality and competitiveness of Synopsys IP offerings through expert problem-solving and continuous improvement.
• Mentoring and developing junior engineers, strengthening the team’s collective expertise and future leadership pipeline.
  
  

What You’ll Need:

• Ph.D. with 6+ years, or M.Sc. with 8+ years of practical analog IC design experience, preferably in Electrical Engineering, Computer Engineering, or a related field.
• Deep expertise in transistor-level circuit design and sound CMOS fundamentals.
• Hands-on design experience with one or more SERDES sub-circuits (e.g., receive equalizers, samplers, drivers, serializers/deserializers, voltage-controlled oscillators, PLLs, bandgap references, ADCs, DACs).
• Proficiency with schematic entry, physical layout, and design verification tools; familiarity with SPICE simulators and simulation methodologies.
• Experience with analog/digital co-design for performance optimization, including calibration, adaptation, and timing handoff.
• Knowledge of reliability and layout effects (EM, IR, aging, matching, proximity, ESD, etc.).
• Proficiency in Verilog-A for analog behavioral modeling, and experience with scripting languages such as TCL, Perl, C, Python, or MATLAB.
• Excellent communication, presentation, and documentation skills.
  
  

Who You Are:

• Innovative thinker with a solutions-oriented approach to complex technical challenges.
• Effective communicator, adept at translating intricate technical details for diverse audiences.
• Collaborative team player who thrives in multidisciplinary environments.
• Natural mentor and leader, committed to supporting and uplifting peers and junior engineers.
• Highly organized, detail-oriented, and proactive in driving project deliverables.
• Resilient and adaptable, embracing new technologies and methodologies with enthusiasm.
  
  

The Team You’ll Be A Part Of:

You’ll join a dynamic, growing analog and mixed-signal design team focused on developing cutting-edge Multi-Gbps SERDES IP. The team is composed of passionate engineers from diverse backgrounds, collaborating closely with digital designers, layout specialists, and software/CAD experts. Our culture emphasizes technical excellence, innovation, and continuous learning. With access to best-in-class design tools and in-house support, this team thrives on solving industry-defining challenges and delivering world-class IP to Synopsys’ global customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.