Sr. Technical Manager, Memory Test and Built-In Self-Test (6762) at TSMC
Date: 4 hours ago
City: Ottawa, ON
Contract type: Full time
Overview Of Role
TSMC Design Technology Canada Inc. is seeking a highly experienced and exceptionally skilled Senior Technical Manager, Design for Test (DFT) and Memory Built-In Self-Test (BIST) to join our world-class team. This is a critical technical leadership role for a ‘Memory Guru’ who will drive innovation and solve complex, unprecedented challenges in cutting-edge memory technologies.
This role is paramount to TSMC's strategic initiatives, especially in the context of the AI and Machine Learning boom, where merging logic and memory for energy-efficient, high-bandwidth solutions is a key bottleneck. The ideal candidate will be a visionary who can control BIST DFT architecture, develop silicon-proven custom BIST solutions for emerging memories, and ensure "first-time-right" silicon on process technologies never used before.
You will leverage your 10+ years of extensive experience in memory testing and self-testing, with a proven track record in advanced memory test algorithms, defect modeling, and state-of-the-art design-for-test methodologies. This position demands a deep understanding of memory circuit design, ASIC design, Compute-in-Memory (CIM), chip design and 2.5D + 3D System-in-Package architectures, coupled with hands-on expertise in EDA tools for Memory BIST (e.g., Synopsys, Mentor/Siemens) and the ability to interact effectively with EDA vendors.
You will play a pivotal role in ensuring the quality and reliability of our memory technologies, collaborating with cross-functional teams in Ottawa and globally (including Taiwan R&D, product, process, and reliability engineering teams) to drive innovation and deliver cutting-edge solutions that enable tens of billions of end products worldwide.
TSMC is the world’s number one semiconductor manufacturer, employing 80,000+ people worldwide and the first company to ramp 5nm & 3nm into mass production while working on next-generation process technologies. We lead the industry in sustainable business practices, caring about environmental impacts, human rights, and ethical conduct.
Why Join Us?
Pioneering Impact: Be at the forefront of merging logic and memory for AI/ML, driving the future of energy-efficient, high-bandwidth computing (e.g. CIM) and at the forefront of 2.5D & 3D chip design.
Architectural Control: Take immediate control and define the direction of Memory BIST DFT architecture. Create Controllers and Test solutions for emerging memory technologies. En
Solve Unprecedented Problems: Tackle challenges no one has seen before, with the resilience and ingenuity to find solutions for "first-time-right" silicon on novel processes.
Global Influence: Work within a dynamic, collaborative environment with direct influence on global TSMC projects and interactions with R&D teams worldwide.
Cutting-Edge Technologies: Gain an inside track to the newest process technologies, 3DIC, and emerging memory types (HBM, SRAM, ROM, eDRAM, MRAM, RRAM, eFlash, OTP, etc.).
Competitive Package: Enjoy competitive compensation, comprehensive benefits, and significant career growth opportunities within a leading global organization.
If you are a seasoned "Memory Guru" with a passion for driving architectural innovation in memory test and design, a proactive problem-solver, and possess the confidence to lead and influence, we invite you to apply and contribute to our mission of delivering world-class memory solutions.
Responsibilities
Strategic Memory BIST DFT Architecture: Define and control the architectural direction for Memory Built-In Self-Test (BIST) and Design-for-Test (DFT) strategies across TSMC's advanced memory offerings.
Advanced Memory Test & Self-Testing: Design, develop, and execute controllers and BIST engines for cutting-edge memory. Develop test algorithms and self-test methodologies for a wide range of memory types (e.g., HBM, CIM, SRAM, MRAM, RRAM, eDRAM, ROM, and novel emerging memories). Lead the development and optimization of memory test flows to ensure highest yield and reliability, specifically focusing on finding and resolving critical defects.
Defect & Fault Modeling & Debugging: Conduct extensive memory defect and fault modeling to identify and address potential failure mechanisms. Implement robust fault detection and diagnosis strategies to enhance memory performance and quality, with a strong emphasis on debugging customer silicon problems and preventing escapes.
Memory-Specific DFT Implementation: Develop and implement highly specialized memory-specific DFT solutions to ensure manufacturability and testability for complex memory designs. Collaborate closely with memory circuit design teams to embed advanced testability features.
EDA & Custom BIST Design Expertise: Utilize and strategically interact with EDA tools for Memory BIST (e.g., Synopsys, Mentor/Siemens, Cadence) to support customer memory IP. Develop silicon-proven, innovative custom BIST solutions for emerging memory architectures, including RTL design, verification, and silicon debug. Proactively negotiate with EDA vendors for new processes and tools as needed.
Memory Circuit Test & Verification Leadership: Provide technical leadership in the design for test and verification of memory circuits, ensuring deep understanding of circuit operation to inform test decisions. Work closely with circuit design teams, including those in Ottawa, to ensure seamless integration of test methodologies and sign-off for FAB databases.
3D/2.5D DFT and Memory Test: Drive the development and implementation of 3D/2.5D DFT and test standards, with critical expertise in 3D memory integration methodology and testing approaches, especially given the rapid expansion of AI.
ASIC and Chip-Level Integration: Contribute to the design and development of CIMs, ASICs and 3D-SoCs, with a deep focus on memory subsystems. Manage chip-level integration and validation of memory-related functions, understanding logic-memory bandwidth challenges.
Cross-Functional & Global Collaboration: Proactively collaborate with internal design teams (ASIC, Memory), external EDA vendors, and global R&D, product, process, and reliability engineering teams. Build trust and strong relationships across the TSMC universe, including regular interaction with TSMC teams around the world and important Customer and EDA vendor support.
Technical Mentorship & Leadership: Provide technical guidance and mentorship to junior engineers, fostering growth and sharing deep domain expertise. Lead complex technical projects involving multiple stakeholders with confidence and a "go out and grab things" personality.
Minimum Qualifications
TSMC Design Technology Canada (TDTC) is in the High-Tech area of Ottawa, Ontario. TDTC is focused on the research and design of deep sub-micron circuits to better serve and support the manufacturing needs of our foundry customers and 3rd party vendors.
TSMC Design Technology Canada Inc, is a wholly owned subsidiary of TSMC in Taiwan.
As a trusted technology and capacity provider, TSMC is driven by the desire to be:
For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, TSMC North America may have to obtain export licensing approval from the U.S. Government for certain individuals. All employment is contingent upon TSMC North America obtaining any export license or other approval that may be required by the U.S. Government.
Diversity statement
TSMC Design Technology Canada Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunities for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, genetic information, or any other characteristic protected by the Employment Equity Act and other application legislation in Canada.
TSMC is an equal opportunity employer embracing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at [email protected] . TSMC confirms to all applicants its commitment to meet TSMC’s obligations under applicable employment law. Reasonable accommodations will be determined on a case-by-case basis.
TSMC Design Technology Canada Inc. is seeking a highly experienced and exceptionally skilled Senior Technical Manager, Design for Test (DFT) and Memory Built-In Self-Test (BIST) to join our world-class team. This is a critical technical leadership role for a ‘Memory Guru’ who will drive innovation and solve complex, unprecedented challenges in cutting-edge memory technologies.
This role is paramount to TSMC's strategic initiatives, especially in the context of the AI and Machine Learning boom, where merging logic and memory for energy-efficient, high-bandwidth solutions is a key bottleneck. The ideal candidate will be a visionary who can control BIST DFT architecture, develop silicon-proven custom BIST solutions for emerging memories, and ensure "first-time-right" silicon on process technologies never used before.
You will leverage your 10+ years of extensive experience in memory testing and self-testing, with a proven track record in advanced memory test algorithms, defect modeling, and state-of-the-art design-for-test methodologies. This position demands a deep understanding of memory circuit design, ASIC design, Compute-in-Memory (CIM), chip design and 2.5D + 3D System-in-Package architectures, coupled with hands-on expertise in EDA tools for Memory BIST (e.g., Synopsys, Mentor/Siemens) and the ability to interact effectively with EDA vendors.
You will play a pivotal role in ensuring the quality and reliability of our memory technologies, collaborating with cross-functional teams in Ottawa and globally (including Taiwan R&D, product, process, and reliability engineering teams) to drive innovation and deliver cutting-edge solutions that enable tens of billions of end products worldwide.
TSMC is the world’s number one semiconductor manufacturer, employing 80,000+ people worldwide and the first company to ramp 5nm & 3nm into mass production while working on next-generation process technologies. We lead the industry in sustainable business practices, caring about environmental impacts, human rights, and ethical conduct.
Why Join Us?
Pioneering Impact: Be at the forefront of merging logic and memory for AI/ML, driving the future of energy-efficient, high-bandwidth computing (e.g. CIM) and at the forefront of 2.5D & 3D chip design.
Architectural Control: Take immediate control and define the direction of Memory BIST DFT architecture. Create Controllers and Test solutions for emerging memory technologies. En
Solve Unprecedented Problems: Tackle challenges no one has seen before, with the resilience and ingenuity to find solutions for "first-time-right" silicon on novel processes.
Global Influence: Work within a dynamic, collaborative environment with direct influence on global TSMC projects and interactions with R&D teams worldwide.
Cutting-Edge Technologies: Gain an inside track to the newest process technologies, 3DIC, and emerging memory types (HBM, SRAM, ROM, eDRAM, MRAM, RRAM, eFlash, OTP, etc.).
Competitive Package: Enjoy competitive compensation, comprehensive benefits, and significant career growth opportunities within a leading global organization.
If you are a seasoned "Memory Guru" with a passion for driving architectural innovation in memory test and design, a proactive problem-solver, and possess the confidence to lead and influence, we invite you to apply and contribute to our mission of delivering world-class memory solutions.
Responsibilities
Strategic Memory BIST DFT Architecture: Define and control the architectural direction for Memory Built-In Self-Test (BIST) and Design-for-Test (DFT) strategies across TSMC's advanced memory offerings.
Advanced Memory Test & Self-Testing: Design, develop, and execute controllers and BIST engines for cutting-edge memory. Develop test algorithms and self-test methodologies for a wide range of memory types (e.g., HBM, CIM, SRAM, MRAM, RRAM, eDRAM, ROM, and novel emerging memories). Lead the development and optimization of memory test flows to ensure highest yield and reliability, specifically focusing on finding and resolving critical defects.
Defect & Fault Modeling & Debugging: Conduct extensive memory defect and fault modeling to identify and address potential failure mechanisms. Implement robust fault detection and diagnosis strategies to enhance memory performance and quality, with a strong emphasis on debugging customer silicon problems and preventing escapes.
Memory-Specific DFT Implementation: Develop and implement highly specialized memory-specific DFT solutions to ensure manufacturability and testability for complex memory designs. Collaborate closely with memory circuit design teams to embed advanced testability features.
EDA & Custom BIST Design Expertise: Utilize and strategically interact with EDA tools for Memory BIST (e.g., Synopsys, Mentor/Siemens, Cadence) to support customer memory IP. Develop silicon-proven, innovative custom BIST solutions for emerging memory architectures, including RTL design, verification, and silicon debug. Proactively negotiate with EDA vendors for new processes and tools as needed.
Memory Circuit Test & Verification Leadership: Provide technical leadership in the design for test and verification of memory circuits, ensuring deep understanding of circuit operation to inform test decisions. Work closely with circuit design teams, including those in Ottawa, to ensure seamless integration of test methodologies and sign-off for FAB databases.
3D/2.5D DFT and Memory Test: Drive the development and implementation of 3D/2.5D DFT and test standards, with critical expertise in 3D memory integration methodology and testing approaches, especially given the rapid expansion of AI.
ASIC and Chip-Level Integration: Contribute to the design and development of CIMs, ASICs and 3D-SoCs, with a deep focus on memory subsystems. Manage chip-level integration and validation of memory-related functions, understanding logic-memory bandwidth challenges.
Cross-Functional & Global Collaboration: Proactively collaborate with internal design teams (ASIC, Memory), external EDA vendors, and global R&D, product, process, and reliability engineering teams. Build trust and strong relationships across the TSMC universe, including regular interaction with TSMC teams around the world and important Customer and EDA vendor support.
Technical Mentorship & Leadership: Provide technical guidance and mentorship to junior engineers, fostering growth and sharing deep domain expertise. Lead complex technical projects involving multiple stakeholders with confidence and a "go out and grab things" personality.
Minimum Qualifications
- 10+ years of extensive, hands-on experience in memory test and memory self-test development, with a proven track record as a "Memory Guru."
- Demonstrated expertise in advanced memory test algorithms and design for test (DFT), with a focus on problem resolution and preventing escapes.
- Significant experience in memory defect and fault modeling, failure analysis, and debugging complex silicon issues.
- Deep understanding of memory circuit design principles and methodologies, with prior hands-on experience that allows for effective interaction with designers.
- Expert proficiency in EDA tools for Memory BIST (e.g., Synopsys, Mentor/Siemens, Cadence) and proven ability to develop custom BIST solutions.
- Strong knowledge of ASIC design, chip design, and integration, particularly concerning memory subsystems and logic-memory interaction.
- Proactive problem-solver with exceptional resilience, initiative, and the ability to tackle novel, undefined problems in cutting-edge technology.
- Excellent negotiation skills for interacting with EDA vendors on new processes and tool requirements.
- Strong written and verbal communication skills , capable of concise technical communication across global teams.
- Advanced degree (M.S. or Ph.D.) in Electrical Engineering, Computer Engineering, or a related field.
- Experience with memory technologies such as HBM memory controllers, RRAM, MRAM or emerging memory.
- Familiarity with advanced semiconductor manufacturing processes and technologies.
- Active participation or interest in industry standards bodies (e.g. IEEE) or technical conferences (e.g., ITC).
- Experience or strong interest in project and technical team management.
TSMC Design Technology Canada (TDTC) is in the High-Tech area of Ottawa, Ontario. TDTC is focused on the research and design of deep sub-micron circuits to better serve and support the manufacturing needs of our foundry customers and 3rd party vendors.
TSMC Design Technology Canada Inc, is a wholly owned subsidiary of TSMC in Taiwan.
As a trusted technology and capacity provider, TSMC is driven by the desire to be:
- The world’s leading dedicated semiconductor foundry
- The technology leader with a strong reputation for manufacturing excellence
- Advancing semiconductor manufacturing innovations to enable the future of technology
For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, TSMC North America may have to obtain export licensing approval from the U.S. Government for certain individuals. All employment is contingent upon TSMC North America obtaining any export license or other approval that may be required by the U.S. Government.
Diversity statement
TSMC Design Technology Canada Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunities for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, genetic information, or any other characteristic protected by the Employment Equity Act and other application legislation in Canada.
TSMC is an equal opportunity employer embracing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at [email protected] . TSMC confirms to all applicants its commitment to meet TSMC’s obligations under applicable employment law. Reasonable accommodations will be determined on a case-by-case basis.
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