ASIC Design Engineer, Power Analysis/Optimization at Qualcomm

Company

Qualcomm Canada ULC

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

What we are doing has not been done.

Shape the future of low power AI subsystems.

Push the boundaries on features and performance.

Qualcomm Technologies Audio products are designed to offer premium wireless connectivity, high levels of integration, immersive sound quality, and on-device AI for smart audio and context aware applications. An ultra-low power subsystem within a low power SoC; a chip-within-a-chip HW block incorporating multiple always-on IP's, design execution within this group requires solving ground-breaking challenges and multiple power domain crossing issues.

As we are pioneer new and/or improved functionality, innovate to minimize power consumption. Make a difference, join a team on the cutting edge and become an integral part of Qualcomm’s growth and momentum.

We are looking for an ASIC Design Engineer who will focus on power optimization to our team as we innovate and design complex leading, ultra-low power, solutions for audio and context aware applications.

The candidate will be responsible for all aspects of tracking power and finding opportunities for improvement. Activities would include:

• Reviewing existing power test case definitions and defining new ones
• Reviewing waveforms for correctness from a power perspective.
• Reviewing PTPX results for both DC and PD netlists
• Reviewing post-silicon power results and correlating with pre-silicon
• Power projection activities, what/if scenario exploration
• Tracking active and leakage power
  
  
  

The role would also call for other design activities from time to time but power would be the primary focus.

Qualifications

• 2-5 years of ASIC hardware design and/or implementation experience.
• Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL.
• Understanding of ASIC/VLSI concepts
• Experience in logic synthesis using Synopsis and/or Cadence tools.
• Ability to work legally in Canada
  
  
  

Preferred Qualifications

• 5 years of ASIC hardware design related experience
• Experience with power analysis, power modeling and low power RTL design.
• Experience with clock domain crossing techniques
• Power and performance experience with an audio IP core, DSP, various audio interfaces (I2S, PCM, SLIMbus, SoundWire, Audio Codec) and accelerators (low-power AI/ML inference).
• Experience with a subset of DC, FC, PTPX, Power Compiler, Primetime, Modeltech, VCS, power theatre, etc.)
• Experience with design rule check (Spyglass, etc.), Formal verification (Formality, LEC, etc.) and/or Power analysis and simulation
• Scripting skills (Python , PERL, TCL or C)
• Knowledge of bus interface protocols (APB, AHB, AXI)
• Experience with post-silicon debug
• Experience with UVM
  
  
  

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
  
  
  

OR

Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

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