Analog Methodology Engineer, Principal

The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP Prototyping Kits and IP subsystems. Our extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. At Synopsys, you will have the opportunity to find the perfect blend of our exceptional EDA presence and our broad IP portfolio.

Our Solution IP group is ramping up high-performance computing (HPC) demand, therefore we are looking for an enthusiastic applicant to join our team. You will be working with a cross functional team of analog and mixed signal circuit designers from a wide variety of backgrounds on design and methodology. This position requires hands on experience with transistor level simulations, reliability analysis, static timing analysis (STA) tools, a vast knowledge of mixed signal circuit design principles, a deep understanding of silicon IP release requirements, strong scripting skills to automate flows and the ability to lead and train junior engineers to become experts with new methodologies.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or similar technical field
• BSEE degree and 18-25 years of experience in IC design, or MSEE (or PhD) with 15-18 years of experience.
• Extensive programming skills in languages such as Python, Perl, TCL and C/C++
• Ability to provide automation for rapid and dynamic design needs is highly sought-after
• Extensive knowledge of Analog & Mixed-Signal circuit design
• Direct design experience in high speed PHY such as SERDES, DDR or HBM is a strong plus
• Proficiency with spice simulators including HSPICE, PrimeSim/FineSim and XA
• Deep knowledge on DC/AC/Transient, Cross corners PVT, Static & Dynamic CCK, Equivalency checks, Aging, EMIR/SHE Reliability analysis, Monte Carlo simulations
• Must be a team player with good written and verbal communication skills, self-motivated, thorough design styles, detail oriented, and work with multiple functional teams with good engineering practices
• Understanding of behavioral Verilog models & experience in SystemVerilog for AMS circuits
• Prior experience on products/test chips bring up, lab debug and simulations to silicon correlation is highly desirable
• Experience with STA and cell characterization such as Nanotime, Primetime, SiliconSmart
• Candidate with Machine Learning paradigms/techniques understandings with knowledge of applying it in modeling, circuit design flow & simulations is desirable
  
  

Should you require an accommodation, please contact [email protected]